View ICS9148-17_90828.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS9148-17
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-17 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Features include four CPU, six PCI, two AGP (=2xPCI) and Twelve SDRAM clocks. Two reference outputs are available equal to the crystal frequency. One 48 MHz for USB, and one 24 MHz clock for Super IO. Built in 1.5%, 0.6% center or down spread spectrum modulation to reduce EMI. Serial programming I2C interface allows changing functions, stop clock programing and frequency selection. Additionally, the device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 505% duty cycle. The REF and 24 and 48 MHz clock outputs typically provide better than 0.5V/ns slew rates.
Features
3.3V outputs: SDRAM, AGP, PCI, REF, 48/24 MHz 2.5V or 3.3V outputs: CPU 20 ohm CPU clock output impedance 20 ohm PCI clock output impedance CPU to PCI skew = 2 to 6ns No external load cap for CL=18pF crystals 250 ps max CPU, PCI clock skew Smooth CPU frequency transition among all CPU frequencies. I2C interface for programming 2ms power up clock stable time Clock duty cycle 45-55%. 48 pin 300 mil SSOP package 3.3V operation, 5V tolerant inputs.
Pin Configuration
Block Diagram
PLL2 /2 X1 X2 XTAL OSC
STOP
48MHz 24MHz REF (0:1) AGP(0:1)
2
PLL1 Spread Spectrum FS(0:2) MODE CPU3.3#_2.5
STOP
4
CPUCLK (0:3)
48-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
CPU_STOP
3
LATCH
PCI CLOCK DIVDER
12
SDRAM (0:11)
5
POR
STOP
5
PCICLK (0:4) PCICLK_F
Power Groups
VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:11), supply for PLL core, 24 MHz, 48MHz VDD4 = AGP (0:1) VDDL = CPUCLK (0:3)
Control CPU_STOP# PCI_STOP# SDATA SCLK Logic Config. Reg.
PCI_STOP
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
9148-17 Rev G 4/27/00
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9148-17
Pin Descriptions
PIN NUMBER 1 2 3,9,16,22,27, 33,39,45 4 5 6,14 7 8 10, 11, 12, 13 15, 47 17 P I N NA M E VDD1 REF0 C P U 3 . 3 # _ 2 . 5 1,2 GND X1 X2 VDD2 PCICLK_F FS11, 2 PCICLK0 FS2
1, 2
TYPE PWR OUT IN PWR IN OUT PWR OUT IN OUT IN OUT OUT IN OUT IN OUT OUT PWR IN IN OUT IN OUT IN OUT PWR OUT PWR
DESCRIPTION Ref (0:2), XTAL power supply, nominal 3.3V 14.318 MHz reference clock. Indicates whether VDDL is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V C P U 1. L a t c h e d i n p u t . Ground. Crystal input, has internal load cap (33pF) and feedback resistor from X2. Crystal output, nominally 14.318MHz. Has internal load cap (33pF). Supply for PCICLK_F and PCICLK (0:4), nominal 3.3V Free running PCI clock Frequency select pin. Latched input PCI clock output. Frequency select pin. Latched input PCI clock outputs. Advanced Graphic Port outputs, powered by VDD4. Halts CPUCLK (0:3) clocks and AGP (0:1) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output Halts PCICLK (0:5) clocks at logic 0 level, when input low (in mobile mode, MODE=0) SDRAM clock output SDRAM clock outputs. Supply for SDRAM (0:11), Core, 24MHz and 48MHz clocks, nominal 3.3V. Data input for I2C serial input. Clock input of I2C input 24MHz output clock. Pin 17, 18 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched input. 48MHz output clock Frequency select pin. Latched input CPU clock outputs, powered by VDDL. Supply for CPU (0:3), either 2.5V or 3.3V nominal 14.318MHz reference clock. Supply for AGP (0:1)
PCICLK (1:4) AGP (0:1) CPU_STOP#1 SDRAM 11
18 20, 21,28, 29, 31, 32, 34, 35,37,38 19,30,36 23 24 25
PCI_STOP#1 SDRAM 10 SDRAM (0:9) VDD3 SDATA SCLK 24MHz MODE1, 2 48MHz FS0
1, 2
26 40, 41, 43, 44 42 46 48
CPUCLK (0:3) VDDL REF1 VDD4
Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
2
ICS9148-17
Mode Pin - Power Management Input Control
MODE, Pin 25 (Latched Input) 0 1 Pin 17 CPU_STOP# (INPUT) SDRAM 11 (OUTPUT) Pin 18 PCI_STOP# (INPUT) SDRAM 10 (OUTPUT)
Power Management Functionality
CPU_STOP# PCI_STOP# AGP, CPUCLK Outputs Stopped Low Running Running PCICLK (0:5) Running Running Stopped Low PCICLK_F, REF, 24/48MHz and SDRAM Running Running Running Crystal OSC Running Running Running VCO
0 1 1
1 1 0
Running Running Running
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5 Input level (Latched Data) 1 0 Buffer Selected for operation at: 2.5V VDD 3.3V VDD
Functionality
VDD1, 2, 3, 4 = 3.3V5%, VDDL = 2.5V 5% or 3.3 5%, TA= 0 to 70C Crystal (X1, X2) = 14.31818MHz
FS2 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0 CPU, SDRAM (MHz) 100.2 90 83.3 75 75 68.5 66.8 60 PCI (MHz) 33.4 30 32 32 37.5 34.25 33.4 30 AG P (MHz) 66.8 60 64 64 75 68.5 66.8 60 R E F, I OA P I C (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
3
ICS9148-17
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 4
6.
ICS9148-17
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit Bit 7 Description 0 - 1.5% Spread Spectrum Modulation 1 - 0.6% Spread Spectrum Modulation Bit 6,5,4 CPU Clock PCI PWD 0 AGP
111 100.2 33.4 66.8 110 90 30 60 Bit 101 83.3 32 64 6:4 100 75 32 64 011 75 37.5 75 010 68.5 34.25 68.5 001 66.8 33.4 66.8 000 60 30 60 0 - Frequency is selected by hardware select, Bit 3 Latched Inputs 1 - Frequency is selected by Bit 6:4 (above) 0 - Spread Spec rum ce e t Bit 2 1 - Spread Specttrum dontnrsspreadtyype. w pread pe. 0 - No a Bit 1 1 - Sprrmd lSpectrum Enabled ea 0R g Bit 0 1- -Triunninall outputs state
Note 1 0,0,0
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if bit 3 is written to a 1 to use bits 6:4, then these should be defined to desired frequency at same write cycle.
Note: PWD = Power-Up Default
0 0 0 0
I2C is a trademark of Philips Corporation
5
ICS9148-17
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 41 43 44 PWD 0 1 1 1 1 1 1 1 Description Version bit (Reserved) (Reserved) (Reserved) CPUCLK3 (Act/Inact) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 15 14 12 11 10 8 PWD 1 1 1 1 1 1 1 Description Latched FS1# PCICLK_F (Act/Inact) AGP0 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0(Act/Inact)
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 34 35 37 38 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 (Act/Inact) SDRAM6 (Act/Inact) SDRAM5 (Act/Inact) SDRAM4 (Act/Inact) SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact)
Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 17 18 20 21 PWD 1 1 1 1 1 1 1 Description Latched FS0# (Reserved) (Reserved) (Reserved) SDRAM11 (Act/Inact) (Desktop Mode Only) SDRAM10 (Act/Inact) (Desktop Mode Only) SDRAM9 (Act/Inact) SDRAM8 (Act/Inact)
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 47 46 2 PWD 1 1 1 1 1 1 1 Description Latched FS2# (Reserved) (Reserved) AGP1(Act/Inact) (Reserved) (Reserved) REF1 (Act/Inact) REF0 (Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency selects will be Inverted logic level of the input frequency select pin conditions.
6
ICS9148-17
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9148-17. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9148-17. 3. All other clocks except CPU and AGP clocks continue to run undisturbed.
7
ICS9148-17
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-17. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9148-17 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
CPUCLK (Internal)
PCICLK (Internal) PCICLK (Free-running) CPU_STOP# (High) PCI_STOP#
PCICLK (External)
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9148. 3. All other clocks continue to run undisturbed.
8
ICS9148-17
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9148-17 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
9
ICS9148-17
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 7.0 V GND 0.5 V to VDD +0.5 V 0C to +70C 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Input frequency Input Capacitance1 Transition Time1 Settling Time Skew
1 1 1 1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP Fi CIN CINX Ttrans Ts TSTAB
CONDITIONS
MIN 2 VSS-0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; 66.8 MHz VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq.
0.1 2.0 -100 100 14.318
MAX VDD+0.3 0.8 5
160
UNITS V V A A A mA MHz
27
36
5 45 2 2
pF pF ms ms ms ps ns
Clk Stabilization
TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads TCPU-PCI1 VT = 1.5 V; CPU Leads
-500 2
200 5
500 6
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Skew1
1
SYMBOL IDD2.5OP
CONDITIONS CL = 0 pF; 66.8 MHz
MIN
TYP 10 200 5
MAX 20 500 6
UNITS mA ps ns
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
-500 2
Guaranteed by design, not 100% tested in production.
10
ICS9148-17
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; C L = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute
1
SYMBOL VOH2A VOL2A IOH2A IOL2A tr2A1 tf2A1 d t2A1 tsk2A1 t j1s2A1 tjabs2A1
CONDITIONS IOH = -28 mA IOL = 27 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.5
33
TYP 2.6 0.35 -29 37 1.75 1.1
MAX 0.4 -23 2 2 55 250 150 250
UNITS V V mA mA ns ns % ps ps ps
45
50 50 65
-250
165
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH2B IOH = -8 mA Output Low Voltage VOL2B IOL = 12 mA Output High Current IOH2B VOH = 1.7 V Output Low Current IOL2B VOL = 0.7 V tr2B1 Rise Time VOL = 0.4 V, VOH = 2.0 V Fall Time Duty Cycle Skew Jitter, Single Edge Displacement2 Jitter, One Sigma Jitter, Absolute
1 2
MIN 2
19
TYP 2.2 0.3 -20 26 1.5 1.6
MAX 0.4 -16 1.8 1.8 55 250 250 150 300
UNITS V V mA mA ns ns % ps ps ps ps
tf2B
1
VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V 40
dt2B1 tsk2B1
47 60 200 65
tjsed2B 1 VT = 1.25 V tj1s2B1 VT = 1.25 V tjabs2B 1 VT = 1.25 V
-300
160
Guaranteed by design, not 100% tested in production. Edge displacement of a period relative to a 10-clock-cycle rolling average period.
11
ICS9148-17
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute
1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 1 tf1
1 1 1
CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, synchronous VT = 1.5 V, asynchronous VT = 1.5 V, synchronous VT = 1.5 V, asynchronous
MIN 2.4
41
TYP 3 0.2 -60 50 1.8 1.6
MAX 0.4 -40 2 2 55 250 150 250 250 650
UNITS V V mA mA ns ns % ps ps ps ps ps
d t1
45
51 130 40 200
tsk1
tj1s1a tj1s1b tabs1a tjabs1b
1
-250 -650
135 500
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS IOH = -28 mA Output High Voltage VOH1 IOL = 23 mA Output Low Voltage VOL1 VOH = 2.0 V Output High Current IOH1 VOL = 0.8 V Output Low Current IOL1 Rise Time1 Tr1 VOL = 0.4 V, VOH = 2.4 V Fall Time1 Tf1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle1 Skew
1
MIN 2.4
41
TYP 3 0.2 -60 50 1.75 1.5
MAX 0.4 -40 2 2 55 500 150 +250 400
UNITS V V mA mA ns ns % ps ps ps ps
Dt1 Tsk1 Tj1s1 Tjabs1 Tjabs1
VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V (with synchronous PCI) VT = 1.5 V (with asynchronous PCI)
45
50 200 50
Jitter, One Sigma1 Jitter, Absolute1 Jitter, Absolute1
1
-250 -400
Guaranteed by design, not 100% tested in production.
12
ICS9148-17
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; C L = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma1 Jitter, Absolute1
1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 1 tf1
1 1 1
CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, synchronous VT = 1.5 V, asynchronous
MIN 2.4
41
TYP 3 0.2 -60 50 1.1 1
MAX 0.4 -40 2 2 55 250 3 5 6
UNITS V V mA mA ns ns % ps % % %
d t1
45
49 130 2
tsk1
tj1s1 tabs1a tjabs1b
-5 -6
2.5 4.5
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz, REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; C L = 10 -20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter, One Sigma Jitter, Absolute
1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5
1 1 1
CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
16
TYP 2.6 0.3 -32 25 2 1.9
MAX 0.4 -22 4 4 57 3 5
UNITS V V mA mA ns ns % % %
d t5
45 -5
54 1 -
tj1s5 1 tjabs5 1
Guaranteed by design, not 100% tested in production.
13
ICS9148-17
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended.
Capacitor Values: C1, C2 : Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01F ceramic
14
ICS9148-17
Ordering Information
ICS9148yF-17-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
15
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

▲Up To Search▲

Price & Availability of ICS9148-17

	To Download ICS9148-17 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .